Mask for crystallizing polysilicon and a method for forming thin film transistor using the mask

ABSTRACT

A mask for forming polysilicon has a first slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, a second slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, a third slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, and a fourth slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width. The slit patterns arranged at the first to fourth slit regions are sequentially enlarged in width in the horizontal direction in multiple proportion to the width d of the slit pattern at the first slit region. The centers of the slit patterns arranged at the first to fourth slit regions in the horizontal direction are placed at the same line. The slit patterns arranged at the respective slit regions in the vertical direction are spaced from each other with a distance of 8*d. Alternatively, the first to fourth slit regions may be arranged in reverse order, or in the vertical direction.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to masks forming a polysilicon(polysilicon) and a method for fabricating a thin film transistor usingthe same and, more particularly, to masks for crystallizing amorphoussilicon into polysilicon.

(b) Description of the Related Art

Generally, a liquid crystal display has two panels with electrodes, anda liquid crystal layer sandwiched between the two panels. The two panelsare sealed to each other by way of a sealer while being spaced apartfrom each other by way of spacers. Voltages are applied to theelectrodes so that the liquid crystal molecules in the liquid crystallayer are re-oriented to thereby control the light transmission. Thinfilm transistors are provided at one of the panels to control thesignals transmitted to the electrodes.

In the usual thin film transistors, amorphous silicon is used to form asemiconductor layer. The amorphous silicon-based thin film transistorbears a current mobility of about 0.5–1 cm²/Vsec. Such a thin filmtransistor may be used as a switching circuit for the liquid crystaldisplay. However, as the thin film transistor involves a low currentmobility, it is inadequate for directly forming a driving circuit on theliquid crystal panel.

In order to overcome such a problem, it has been proposed that thepolysilicon bearing a current mobility of about 20–150 cm²/Vsec shouldbe used to form the semiconductor layer. As the polysilicon thin filmtransistor involves a relatively high current mobility, a Chip In Glasswhere the liquid crystal panel has a built-in driving circuit can berealized.

In order to form the polysilicon thin film transistor, it has beenproposed to employ a technique of directly depositing a polysiliconlayer onto a substrate at high temperature, a technique of depositing anamorphous silicon layer onto a substrate and crystallizing the depositedamorphous silicon layer at 600° C., or a technique of depositing anamorphous silicon layer onto a substrate and heat-treating the depositedamorphous silicon layer using laser. However, as such techniques requirehigh temperature processing, it becomes difficult to employ thetechniques for use in processing a liquid crystal panel glass substrate.Furthermore, the uniformity related to the electrical characteristics ofthe neighboring thin film transistors is deteriorated due to thenon-uniform crystalline particle system.

In order to solve such a problem, a sequential lateral solidification(or crystallization) process where the size distribution of the grainsof the polysilicon can be controlled in an artificial manner has beendeveloped. This is a technique based on the fact that the grains of thepolysilicon are grown perpendicular to the interface between thelaser-illuminated liquid phase region and the non-illuminated solidphase region. The laser beams pass through the slit-patternedtransmission region of the mask, and completely melt the amorphoussilicon to thereby form a slit-shaped liquid phase region at theamorphous silicon layer. Thereafter, the liquid phase amorphous siliconis crystallized while being cooled. The growth of the crystal grainsbegins from the boundary of the solid phase region where the laser isnot illuminated while proceeding perpendicular thereto. The graingrowths stop at the center of the liquid phase region while meetingthere. Such a process is repeated while moving the mask slits in thegrowing direction of the grains so that the sequential lateralsolidification can be made throughout the entire target area.

However, in case the slit width of the mask is too large, the graingrowth beginning from the boundary of the slit does not proceed up tothe center of the slit so that small sized particles may be formed atthe center of the slit by way of homogeneous nucleation. In order tosolve such a problem, the slit-patterned area may be divided into twodifferent regions such that the slit patterns arranged at the tworegions are deviated from each other, thereby making the desiredcrystallization.

However, even with the use of such a technique, the size of the grainsof the crystalline particles cannot exceed that of the slit patterns andhence, it is yet limited to control the crystalline particle size in adesired manner.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a polysiliconformation mask for fabricating a thin film transistor which can controlthe grain size of the polysilicon layer in an appropriate manner.

This and other objects may be achieved by a polysilicon formation maskwith a plurality of slit patterns for defining transmission regions oflaser beams to be illuminated. The slit patterns are sequentiallyreduced or enlarged in width in a predetermined direction.

The slit patterns are arranged at two or more different regions, and theslit patterns arranged at the same region have the same width. Thecenters of the slit patterns arranged at the different regions in thepredetermined direction are placed at the same line. The width of theslit patterns arranged in the predetermined direction is in multipleproportion to the minimal slit pattern width.

In a method of fabricating a thin film transistor using such a mask, asequential lateral solidification process is made with respect to anamorphous silicon layer while moving the mask by the width of each slitpattern region in the predetermined direction.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete appreciation of the invention, and many of the attendantadvantages thereof, will be readily apparent as the same becomes betterunderstood by reference to the following detailed description whenconsidered in conjunction with the accompanying drawings in which likereference symbols indicate the same or the similar components, wherein:

FIG. 1 schematically illustrates a sequential lateral solidificationprocess where amorphous silicon is crystallized into polysilicon throughilluminating laser thereto;

FIG. 2 illustrates the micro-structure of polysilicon during the processwhere amorphous silicon is crystallized into the polysilicon through thesequential lateral solidification;

FIG. 3 is a plan view illustrating the structure of a polysiliconformation mask for crystallizing amorphous silicon into polysiliconaccording to a preferred embodiment of the present invention;

FIGS. 4A to 4D illustrate the micro-structure of polysilicon during theprocess where amorphous silicon is crystallized into the polysiliconthrough the sequential lateral solidification based on the mask for thepolysilicon shown in FIG. 3;

FIG. 5 is a cross sectional view of a polysilicon thin film transistoraccording to a preferred embodiment of the present invention; and

FIGS. 6A to 6E sequentially illustrate the steps of fabricating thepolysilicon thin film transistor shown in FIG. 4.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of this invention will be explained with referenceto the accompanying drawings.

FIG. 1 schematically illustrates a sequential lateral solidificationprocess where amorphous silicon is crystallized into polysilicon, andFIG. 2 illustrates the micro-structure of the polysilicon during theprocess.

As shown in FIG. 1, an amorphous silicon layer 200 is formed on aninsulating substrate, and laser beams are illuminated onto the amorphoussilicon layer 200 through a mask 300 with a slit-patterned lighttransmission region 310. The amorphous silicon layer 200 is completelymelted in a local manner, and a liquid phase region 210 is formed at theamorphous silicon layer 200 corresponding to the light transmissionregion 310 of the mask 300. At this time, the grains of the polysiliconare grown from the interface between the laser-illuminated liquid phaseregion 210 and the non-illuminated solid phase region 220 perpendicularthereto. The grain growths stop at the center of the liquid phase regionwhile meeting there. When the laser beams are illuminated onto theamorphous silicon layer 200 while moving the mask slit pattern in thegrowing direction of the grains, the lateral grain growths continuouslyproceed so that the desired grain sizes can be determined.

FIG. 2 illustrates the grain structure of the polysilicon when thesequential lateral solidification process is made using a mask with aslit pattern proceeding in the horizontal direction. It can be knownfrom the drawing that the grains are grown perpendicular to the slitpattern.

In this preferred embodiment, in order to grow the grains in thehorizontal direction or in the vertical direction to bear the desiredsize, the slit pattern is gradually enlarged or reduced in width in thehorizontal direction or in the vertical direction.

FIG. 3 is a plan view of a polysilicon formation mask for crystallizingamorphous silicon into polysilicon.

As shown in FIG. 3, the mask 100 has a first slit region 101 where aplurality of horizontal slit patterns 11 are arranged in the verticaldirection while bearing the same width, a second slit region 102 where aplurality of horizontal slit patterns 12 are arranged in the verticaldirection while bearing the same width, a third slit region 103 where aplurality of horizontal slit patterns 13 are arranged in the verticaldirection while bearing the same width, and a fourth slit region 104where a plurality of horizontal slit patterns 14 are arranged in thevertical direction while bearing the same width. The slit patterns 11 to14 arranged at the first to fourth slit regions 101 to 104 aresequentially enlarged in width in the horizontal direction in multipleproportion to the width d of the slit pattern 11 at the first slitregion 101. The centers of the slit patterns 11 to 14 arranged at thefirst to fourth slit regions 101 to 104 in the horizontal direction areplaced at the same line. The slit patterns 11 to 14 arranged at therespective slit regions 101 to 104 in the vertical direction are spacedfrom each other with a distance of 8*d.

Alternatively, the first to fourth slit regions 101 to 104 may bearranged in reverse order, or in the vertical direction. Of course, itis also possible that the number of slit regions may be increased tobear slit patterns with a width of more than 4 d, or decreased to bearslit patterns with a width of less than 4 d. In this case, the distancebetween the slit patterns at each slit region is altered accordingly.

The sequential lateral solidification process is made with respect tothe amorphous silicon layer 200 by illuminating laser beams onto thetarget area through the mask while moving the mask by the width A of therespective slit regions 101 to 104 being ¼ of the mask length. At thistime, the amorphous silicon layer 200 suffers laser illumination throughthe respective slit regions 101 to 104. With the laser illumination, thecrystalline particles of the amorphous silicon layer 200 are grownperpendicular to the boundary of the slit patterns. This process will benow explained with reference to FIGS. 4A and 4B.

FIGS. 4A and 4B illustrates the structure of the grains grown in thesequential lateral solidification process using the polysiliconformation mask shown in FIG. 3.

In case the laser is illuminated through the fourth slit region 104, asshown in FIG. 4A, a liquid phase region is formed at the amorphoussilicon layer 200 corresponding to the fourth slit region 104, and thecrystalline particle grains are grown from the interface between theliquid phase region and the solid phase region perpendicular thereto by½*d.

Thereafter, the mask 100 moves by the slit region width A, and laser isilluminated through the third slit region 103. Consequently, as shown inFIG. 4B, the particles grown in the previous processing step become tobe seeds, and the crystalline particle grains are again grown by ½*d sothat the particle length becomes to be d.

Thereafter, the mask 100 moves by the slit region width A, and laser isilluminated through the second slit region 102. In the same way, themask 100 moves by the slit region width A, and laser is illuminatedthrough the first slit region 101. Consequently, as shown in FIGS. 4Cand 4D, the particles grown in the previous processing steps become tobe seeds, and the crystalline particles grains are again grown by ½*d sothat the particles length becomes to be 3/2*d, and finally to be 2*d.

Like the above, when the first sequential lateral solidification processis made while moving the mask 100 from the left to the right, a multiplycrystallized area where the crystalline particle length is 2d, and anon-crystallized area with a width of 4d corresponding to the areabetween the slit patterns are resulted. Thereafter, the mask 100 movesin the vertical direction by 4d such that the first to fourth slitregions 101 to 104 correspond to the non-crystallized area. In thisstate, the second sequential lateral solidification process is madewhile moving the mask from the right to the left. Consequently, theparticles formed at the first sequential lateral solidification processbecome to be seeds, and the crystalline particle grains are again grownby 2d at the second sequential lateral solidification process so thatthe particle length becomes to be 4d.

In case nth slit region is present at the mask and the sequentiallateral solidification process is repeatedly made through the mask, theresulting polysilicon particles have a length of n*d.

A method of fabricating a thin film transistor using the mask will benow explained in detail.

FIG. 5 is a cross sectional view of a polysilicon thin film transistoraccording to a preferred embodiment of the present invention, and FIGS.6A to 6E sequentially illustrate the steps of fabricating thepolysilicon thin film transistor. These processing steps may be wellapplied for use in the method of fabricating a semiconductor device fordesigning a driving IC on the liquid crystal panel.

As shown in FIG. 5, a semiconductor layer 20 is formed on an insulatingsubstrate 10 with polysilicon while bearing a channel region 21, andsource and drain regions 22 and 23 formed at both sides of the channelregion 21. The source and the drain regions 22 and 23 are doped with nor p type impurities. The source and the drain regions 22 and 23 maycontain a silicide layer. A gate insulating layer 30 is formed on thesubstrate 10 with silicon oxide SiO₂ or silicon nitride SiN_(x) whilecovering the semiconductor layer 20. A gate electrode 40 is formed onthe gate insulating layer 30 over the channel region 21. Aninter-layered insulating layer 50 is formed on the gate insulating layer30 while covering the gate electrode 40. The gate insulating layer 30and the inter-layered insulating layer 50 have contact holes 52 and 53exposing the source and the drain regions 22 and 23 of the semiconductorlayer 20. A source electrode 62, and a drain electrode 63 facing thesource electrode 62 around the gate electrode 40 are formed on theinter-layered insulating layer 50 such that the source electrode 62 isconnected to the source region 22 through the contact hole 52, and thedrain electrode 63 is connected to the drain region 23 through thecontact hole 53. A protective insulating layer 70 covers theinter-layered insulating layer 50 while bearing a contact hole 73exposing the drain electrode 63. A pixel electrode 80 is formed on theprotective insulating layer 70 with indium tin oxide (ITO), indium zincoxide (IZO) or a reflective conductive material while being connected tothe drain electrode 63 through the contact hole 73.

In a method of fabricating the thin film transistor array substrate, asshown in FIG. 6A, an amorphous silicon layer is deposited onto asubstrate 10 through low pressure chemical vapor deposition, plasmachemical vapor deposition, or sputtering.

Thereafter, as shown in FIG. 6B, laser beams are illuminated onto theamorphous silicon layer through the mask shown in FIG. 3 to thereby forma liquid phase region at the amorphous silicon layer. A sequentiallateral solidification process is made with respect to the amorphoussilicon layer with the liquid phase region while growing the crystallineparticle grains to thereby form a polysilicon semiconductor layer 20.The crystalline particles of the polysilicon semiconductor layer 20 beara sufficiently large size so that the current mobility of the resultingthin film transistor can be maximized.

As shown in FIG. 6C, n or p type impurities are ion-implanted into thesemiconductor layer 20 using the gate electrode 40 as a mask, andactivated to thereby form source and drain regions 22 and 23. The regionbetween the source and the drain regions 22 and 23 is defined as achannel region 21.

As shown in FIG. 6D, an inter-layered insulating layer 50 is formed onthe gate insulating layer 30 such that it covers the gate electrode 40.The inter-layered insulating layer 50 is patterned together with thegate insulating layer 30 to thereby form contact holes 52 and 53exposing the source and the drain regions 22 and 23 of the semiconductorlayer 20.

As shown in FIG. 6E, a metallic layer is deposited onto the substrate10, and patterned to thereby form source and drain electrodes 62 and 63such that the source and the drain electrodes 62 and 63 are connected tothe source and the drain regions 22 and 23 through the contact holes 52and 53, respectively.

Thereafter, as shown in FIG. 5, a protective insulating layer 70 isdeposited onto the inter-layered insulating layer 50 overlaid with thesource and the drain electrodes 62 and 63, and patterned to thereby forma contact hole 73 exposing the drain electrode 63. Then, a conductivelayer based on a transparent conductive material such as ITO and IZO ora reflective conductive material is deposited onto the protectiveinsulating layer 70, and patterned to thereby form a pixel electrode 80.The pixel electrode 80 is connected to the drain electrode 63 throughthe contact hole 73.

As described above, amorphous silicon is crystallized into polysiliconusing a polysilicon mask with slit patterns sequentially enlarged inwidth so that the particle size of the polysilicon can be controlled inan appropriate manner. In this way, the current mobility of thepolysilicon thin film transistor can be maximized.

While the present invention has been described in detail with referenceto the preferred embodiments, those skilled in the art will appreciatethat various modifications and substitutions can be made thereto withoutdeparting from the spirit and scope of the present invention as setforth in the appended claims.

1. A method of fabricating a thin film transistor, the method comprisingthe steps of: depositing an amorphous silicon layer onto an insulatingsubstrate; forming a semiconductor layer through crystallizing theamorphous silicon layer through a sequential lateral solidificationprocess using a polysilicon formation mask where slit patterns fordefining light transmission regions are arranged while beingsequentially reduced or enlarged in width in a predetermined direction;forming a gate insulating layer on the substrate such that the gateinsulating layer covers the semiconductor layer; forming a gateelectrode on the gate insulating layer over the semiconductor layer;forming source and drain regions at the semiconductor layer throughimplanting impurities into the semiconductor layer; forming aninter-layered insulating layer such that the inter-layered insulatinglayer covers the gate electrode; etching the inter-layered insulatinglayer and the gate insulating layer to thereby form contact holesexposing the source and the drain regions; and forming source and drainelectrodes such that the source and the drain electrodes are connectedto the source and the drain regions through the contact holes.
 2. Themethod of claim 1, further comprising the step of forming a pixelelectrode such that the pixel electrode is connected to the drainelectrode.
 3. The method of claim 2, wherein the pixel electrode isformed with a transparent conductive material or a reflective conductivematerial.
 4. The method of claim 1, wherein the slit patterns arearranged at two or more different regions such that the slit patterns atthe same region have the same width, and the sequential lateralsolidification process is made while moving the mask by the width ofeach region in the predetermined direction.